The present invention relates to a microprogram control method and an apparatus therefor having a microprogram memory with an instruction decoding function, in which, more particularly, the microprogram memory is arranged to store short word length microinstructions and to detect an abnormal microprogram sequence.
In the microprogram control system, all of the control items are stored in the microprogram memory. Accordingly, the contents of the memory may be updated to allow a different execution than the old one previously stored.
On the other hand, in order to execute a different instruction set, the contents of an instruction decoder must also be modified. However, since the instruction decoder is usually constructed to comply with a particular instruction set, a sufficiently large scale decoder circuit must be provided or troublesome modification of the circuit configuration is required in order to execute a completely different instruction set.
The present invention permits the flexibility to operate with a different instruction set without losing generality so that the microprogram control system can be used for general purpose while a memory capacity for storing the microprograms can be reduced and also it has a function to detect an abnormal microprogram sequence.
In an instruction fetch microroutine, an instruction word is read out of a main memory and an instruction decoder decodes it to generate an initial address of a microroutine corresponding to that instruction. The generated initial address is stored in a microprogram address register through address selection means, and a microinstruction word specified by the register is read out of a microprogram memory. An operation field (code) of the read-out microinstruction is stored in a microinstruction register and an address field (code) of the microinstruction is returned to the address selection means. The operation field (code) of the microinstruction is decoded by a microinstruction decoder, which generates various control signals. On the other hand, the content of the address field of the microinstruction returned to the address selection means is transferred to a microprogram address register to sequentially read out and execute the microinstructions. The above is an example of a prior art system.
In the system, a time period from the decode of the instruction to the generation of the initial address is mainly determined by the access time of the memory, although it may vary depending on the configuration and the scale of the instruction decoder. In this system, therefore, the configuration of the instruction decoder governs the operation speed of the processor.
Another known system is a mapping system. Such a system is in many cases used in a computer having a simple instruction set. In this system, a fixed bit pattern generating means is provided and an output signal from the bit pattern generating means and the contents of an instruction register which stores the word read out of the main memory are combined to generate an initial address of a microroutine. This system may be called a simplified system in that it does not use an instruction decoder. While this system needs shorter time than the previously mentioned system to establish the output of the microprogram address register, it is not a general purpose system because it cannot be used for a system with a complex instruction set having two or more instruction codes because a branch-to address to the instruction code is fixed in this system.
Furthermore, where a plurality of instruction codes have a common operation, the capacity of the microprogram memory increases because the branch-to addresses are different. In this sense, this system is not a practical one. The above two prior art systems will be further discussed later.
A method for reading a microprogram is disclosed in U.S. Pat. No. 4,008,462 entitled "Plural Control Memory System with Multiple Microinstruction Readout". It discloses a control system which permits the readout of the microinstructions at the same speed as that of the microinstruction readout in a prior art system, even with a low performance control memory. However, this method is applicable only to a system having a control memory bank which reads out a plurality of microinstructions by a single address designation.